1. Field of Invention
The present invention relates to a non-volatile memory device and a method for manufacturing the same, and more particularly, to a non-volatile memory device using FinFETs (Fin-type Field Effect Transistors) and a method for manufacturing the same.
2. Description of Prior Art
Non-volatile memory (NVM) may hold data information in a power off state and thus is widely used. A typical non-volatile memory comprises an MOSFET (Metal Oxide Semiconductor Field Effect Transistor) having a floating gate, and may represent digit “0” or “1” by the amount of charges stored in the floating gate.
Typically, a non-volatile memory comprises cells arranged in an array to provide required memory capacity. For a certain area of a chip, the memory has larger capacity with the increase of the density of the memory. The memory capacity of a non-volatile memory depends on a novel device structure (having a reduced size of a memory cell) with respect to one aspect, and on improvement of microelectronic fabrication technique (which indicates the reduction of the minimum feature size that may be achieved in practice).
However, short channel effects may occur with the scaling of MOSFETs.
Cheming Hu et al. proposed an FinFET formed on an SOI (Silicon-On-Insulator) substrate in U.S. Pat. No. 6,413,802, which comprises a channel region provided in a central portion of a fin of semiconductive material, and source/drain regions provided on both sides of the fin. A gate electrode is provided at both sides of the channel region and surrounds it to provide, for example, a double-gate FinFET, in which inversion layers are created at both sides of the channel. The channel region in the fin has a small thickness so that the whole channel region is controlled by the gate, which suppresses the short channel effect.
The present inventor proposed an NVM using an FinFET in U.S. Pat. No. 7,087,952, which has a control gate at one side of a semiconductor fin and a floating gate at the other side of the semiconductor fin.
In such a floating-gate type memory device, charges tunnel through a floating gate dielectric layer from a substrate to a floating gate, and are then stored in the floating gate. The charges may bei hold even in a case that the memory device is in a power off state. The threshold voltage (Vth) of the FinFET is determined by the amount of charges, and logic “1” and “0” may be distinguished from each other.
Such a non-volatile memory alleviates the negative effect of the short channel effect on the threshold voltage by using an FinFET, and thus has an improved reliability and durability.
However, both the control gate and the floating gate of the non-volatile memory device are provided in Front-End-Of-Line (FEOL), which increases the complexity of the fabrication process and is less cost effective.